A problem occurring in CMOS integrated circuit devices is a parasitic effect called "latch-up." Latch-up can be triggered by transient currents or voltages within the integrated circuit device during power up. The problem of latch-up has been controlled to some extent through the use of improved fabrication processes and by fabricating latch-up prevention mechanisms in the integrated circuit structures. However, most known latch-up prevention mechanisms are not effective in applications in which the substrate of the integrated circuit device is pumped to a negative back bias potential in use of the device.
FIG. 1, which is labeled "PRIOR ART," is a cross section of a portion of an integrated circuit device having an n-well structure 10 with a pumped substrate back bias VBB being applied to the substrate 12. On any given design for an integrated circuit device, such as that illustrated in FIG. 1, a parasitic capacitance exists between the supply voltage terminal VCC of the integrated circuit device and the substrate as a result of semiconductor junctions, primarily n-well to substrate junctions. Moreover, a parasitic capacitance exists between the ground supply terminal VSS of the integrated circuit device and the substrate as a result of semiconductor junctions, primarily n-MOS to substrate junctions.
Referring additionally to FIG. 2, which is also labeled "PRIOR ART," these parasitic capacitances, represented by capacitors Cw and Cs, form a capacitive divider between a regulated voltage VCC, derived from an external supply voltage VCCX (FIG. 3), and the substrate. During power up, the capacitive divider formed by the parasitic capacitances Cw and Cs, causes the substrate 12 to couple above ground (VSS) until such time as the substrate bias pump that produces the back bias voltage VBB can turn on and begin to drive the substrate 12 negative.
The relationship between the back bias voltage VBB and the regulated supply voltage VCC is illustrated in FIG. 3. As there shown, at power up, the substrate voltage VBB rises until the substrate back bias is able to drive the substrate negative. If the substrate 12 couples positive to the point that pn junctions of the integrated circuit device become forward biased, then latch-up will occur.
Latch-up can also occur when the pumped voltage VCCP, that is used for biasing n-well regions formed in integrated circuit memory devices, is less than the supply voltage VCC by at least one Vt, the threshold voltage for a pn diffusion junctions existing between an n-well and the p active area within the n-well. Accordingly, NMOS diode clamps are used to prevent the pumped voltage VCCP and the voltage on the associated n-wells from falling more than one Vt below the supply voltage VCC. However, the pn junctions forward bias around 700 millivolts and the threshold voltage Vt for NMOS diodes is about 800 to 900 millivolts. Thus, the diffusion junctions can become forward biased before the threshold voltage for the NMOS diode is reached, particularly under power-up conditions.
The phenomenon of latch-up is well understood, and many approaches have to be implemented to control or even eliminate latch-up. For example, a method of construction of a diode clamp for averting forward biasing of a parasitic pnp transistor of a semiconductor device is disclosed in an article appearing in the IBM Technical Disclosure Bulletin, Vol. 29, No. 5, October 1986, page 1967 and which is entitled "Prevention Of CMOS Circuit Latch-Up." In making the device, the chip is processed to the point of source/drain formation using standard processes. A mask is then applied to the chip surface to expose only the p-channel drain. Then, the drain is etched with anisotropic chemical etchants and coated with titanium silicide to form a Schottky diode. The Schottky diode is connected to shunt the emitter-base circuit of the parasitic pnp transistor to prevent the emitter-base junction of the parasitic pnp transistor from being biased into an active mode. However, this arrangement does not provide protection against latch-up for integrated circuit devices that have their substrates coupled to a substrate bias source that maintains the substrate at a negative potential in use of the device. Moreover, producing this device requires the use of a separate mask and requires additional process steps which increases the cost of fabricating the integrated circuit device.
Thus, although latch-up prevention mechanisms have been proposed for preventing latch-up in integrated circuit devices, most known latch-up prevention mechanisms are not effective in applications in which the substrate of the integrated circuit device is pumped to a negative back bias potential in use of the device.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a method and integrated circuit structure for preventing pn junctions of integrated circuit devices from becoming forward biased during power-up to prevent latch-up of integrated circuit devices that are operated with a negative substrate bias, or a boosted n-well bias, and which have minimal impact on the fabrication process and do not significantly increase the cost for fabricating such integrated circuit devices.